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Timing And Cadence

Machines expose state over time.

Core Idea

A single artifact is rarely enough. Period, silence, jitter, burst shape, request cadence, response latency, and file timestamp all change what a decode means. Timing is not decoration around bytes; it is part of the evidence.

Timing Shapes

Shape Example Observer question
Periodic broadcast CAN/J1939/NMEA 0183 repeated updates Is this fresh, stale, missing, or mode-dependent?
Arbitration delay CAN lower-priority frames Did bus pressure distort apparent period?
Poll/response Modbus RTU, UDS, OBD-II What did the initiator choose to reveal?
Scheduled slot LIN, FlexRay, TTEthernet Was a slot skipped or merely idle?
Transaction window MIL-STD-1553 Did the expected status or data arrive in order?
Capture timestamp MDF, PCAP, BLF, ASC Is the log clock trustworthy and aligned?

Visual Model

flowchart LR artifact["One artifact"] --> cadence["Repeated timing"] cadence --> freshness["Freshness / stale data"] freshness --> inference["State hypothesis"] capture["Capture clock"] --> freshness

Cadence Discipline

  • Always distinguish event time, capture time, log-write time, and analysis time when the format exposes them.
  • Treat missing messages as evidence with multiple explanations: sleep, failure, bus-off, capture loss, gateway filtering, schedule change, or normal state transition.
  • Treat repeated identical values as ambiguous: stable physical state, stale transmitter, cached response, quantization, or gateway replay.
  • Treat request-driven visibility differently from broadcast telemetry.

Protocol Connections

CAN teaches arbitration pressure. UART teaches sampling phase. Modbus RTU teaches silence gaps and polling cadence. ARINC 429 teaches label update rates. MIL-STD-1553 teaches transaction timing and status response. MDF teaches that logged measurements have metadata and time-base authority.

Binder Rule

Every Tier 1 page should state which timing assumptions matter and how wrong timing creates wrong conclusions.